The present invention relates to design for testability and test sequence generation for integrated circuits (LSIs). More particularly, it relates to techniques to design for testability for an RTL circuit, that is, an integrated circuit designed at register transfer level (RTL).
A typical example of the conventional method of design for testability includes scan design. In the scan design, a flip-flop (FF) included in a logically designed LSI is replaced with a scan FF which can be externally directly controlled (scanned in) and observed (scanned out), so that a problem of a sequential circuit can be simplified into a problem of test pattern generation of a combinational circuit. Thus, test sequences can be easily generated ("Digital Systems Testing and Testable DESIGN, Chapter 9, Design For Testability", 1990, published by Computer Science Press).
The conventional scan design includes full scan design in which all FFs are replaced with scan FFs and partial scan design in which merely FFs difficult to observe and control are replaced with scan FFs so as to overcome problems such as increase in hardware overhead occurring in the full scan design, both of which are executed mainly at gate level.
However, according to the conventional partial scan design at gate level, an operation timing of a gate level circuit generated through the logic synthesis can be harmfully affected by the scan design, so that a normal operation cannot be guaranteed. Therefore, re-design of the circuit is required, which can cause a problem that the design takes a long period of time.
As a countermeasure, partial scan design at register transfer level (RTL) with higher abstraction than the gate level is recently proposed.
For example, in an integrated circuit designed at RTL (i.e., an RTL circuit), registers to be made scannable (hereinafter referred to as scannable registers) are selected by using a testability measure or the like within a specified range of scan ratio (1995, ASPDAC (Asia and South Pacific Design Automation Conference), pp. 209-216, "Design For Testability Using Register Transfer level Partial Scan Selection").
However, in the partial scan design at RTL, it is difficult to achieve high fault coverage at RTL. Specifically, in the RTL partial scan design, the fault coverage is to be increased as far as possible within the specified range of scan ratio, and therefore, it is necessary to repeat a series of procedures of selection of registers to replace with scan registers, logic synthesis, insertion of a scan path and test sequence generation until high fault coverage is achieved. Accordingly, the entire scan design requires a long period of time, resulting in disadvantageously increasing a cost for the design for testability.